Citation Details

My profile on Google Scholar contains many useful details. And my ORCID id is: 0000-0002-3741-0201.

BOOKS and BOOK CHAPTERS

  • Chapter: Gaming with Purpose: Heuristic Understanding of Ubiquitous Game Development and Design for Human Computation Lindsay Grace and Peter Jamieson. IEEE Handbook of Digital Games (ISBN: 978-1-118-32803-3). Editors M. Angelides and H. Agius. Wiley-IEEE Press - 2014 [link]. Book cover

Journal Papers

  • Advancing genetic algorithm approaches to field programmable gate array placement with enhanced recombination operators Robert Collier, Christian Fobel, Ryan Pattison, Gary Grewal, Shawki Areibi, and Peter Jamieson. Journal of Evolutionary Intelligence. October 2014. [link]
  • Analyzing System-Level Information's Correlation to FPGA Placement Farnaz Gharibian, Lesley Shannon, Peter Jamieson, and Kevin Chung. ACM Transactions on Reconfigurable Technology and Systems. Vol. 6. Number 3. October 2013. [link]
  • Power consumption benchmarking for reconfigurable platforms. Teemu Pitkanen, Peter Jamieson, Tobias Becker, Sami Moisio, amd Jarmo Takala. Analog Integrated Circuits and Signal Processing [link]
  • VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling. Jason Luu, Ian Kuon, Peter Jamieson, Ted Campbell, Andy Ye, Mark Fang, and Jonathan Rose, ACM Transactions on Reconfigurable Technology and Systems. Vol. 4. Number 4. December 2011. [link]
  • Enhancing the Area Efficiency of FPGAs With Hard Circuits Using Shadow Clusters. Peter Jamieson and Jonathan Rose IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Vol. 18. Number 12, pp 1696 -1709, 2010 [link]
  • Benchmarking and Evaluating Reconfigurable Architectures in the Mobile Domain. Peter Jamieson, Tobias Becker, Teemu Pitkanen, Peter Y.K Cheung, Wayne Luk, and Tero Rissa ACM Transactions on Design Automation of Electronic Systems. Vol. 15. Number 2, pp 1-24, 2010 [link]
  • Power Characterisation for Fine-Grain Reconfigurable Fabrics. Tobias Becker, Peter Jamieson, Wayne Luk, Peter Cheung, and Terro Rissa. International Journal of Reconfigurable Computing, vol. 2010, Article ID 787405, 9 pages, 2010. doi:10.1155/2010/787405. [link]
  • Using System Emulation to Model Next-generation Shared Virtual Memory Clusters. Angelos Bilas, Courtney R. Gibson, Reza Azimi, Rosalia Christodoulopoulou, and Peter Jamieson. Special Issue of Cluster Computing: the Journal of Networks, Software Tools and Applications. June 2002. [pdf]

REFEREED CONFERENCES

  • Transforming Ladder Logic to Verilog for FPGA Realization of Programmable Logic Controllers. Giancarlo Corti, Drake Brunner, Naoki Mizuno, and Peter Jamieson. ESCS 2017 [link]. Las Vegas, NV. [pdf]
  • Class Behavior on Quizzes that include a Prisoner's Dilemma Bonus Question. Peter Jamieson. FECS 2017 [link]. Las Vegas, NV. [pdf]
  • verilogTown - Improving Students Learning Hardware Description Language Design - Verilog - with a Video Game. Peter Jamieson, Lindsay Grace, Boyu Zhang, and Naoki Mizuno. ASEE 2017 [link]. Columbus, OH. [pdf]
  • A simple Multiplayer Video Game Framework for Experimenting and Teaching Cultural Understanding. Peter Jamieson, Lindsay Grace, Naoki Mizuno, Chris Bell, and Darrel Davis. Academic Mindtrek [link]. Tampere, Finland. [pdf]
  • A Framework to Help Analyze if Creating a Game to Teach a Learning Objective is Worth the Work. Peter Jamieson and Lindsay Grace. FIE'16, 2016 [link]. Erie, PA. [pdf]
  • Improved Method for Creating Criterion Maps for Automatic Mind Map Analysis. Amber Franklin, Chris Bell, Ryan Sunderhaus, and Peter Jamieson. FIE'16, 2016 [link]. Erie, PA. [pdf]
  • VerilogTown: Cars, Crashes and Hardware Design. Lindsay Grace, Peter Jamieson, Boyu Zhang, and Naoki Mizuno. ACE'15, 2015 [link]. Iscandar, Malaysia. [pdf]
  • How to use Combinatorial Optimization Problems (Travelling Salesman Problem) for Procedural Landscape Generation. Alan Ehret, Peter Jamieson, and Lindsay Grace. GAME-ON'15, 2015 [link]. Amsterdam, Netherlands. [pdf]
  • Evaluating Metrics for Automatic Mind Map Assessment in Various Classes. Amber Franklin, Peter Jamieson, Tuo Li, Julie Semlak, and Walter Vanderbush. FIE'15, 2015 [link]. El Paso, TX. [pdf]
  • More Missing the Boat - Arduino, Raspberry Pi, and Small Prototyping Boards and Engineering Education Needs Them. Peter Jamieson and Jeff Herdtner. FIE'15, 2015 [link]. El Paso, TX. [pdf]
  • Identifying and Placing Heterogeneously-sized Cluster Groupings Based on FPGA Placement Data. Farnaz Gharibian, Lesley Shannon and Peter Jamieson. 24th International Conference on Field Programmable Logic and Applications (FPL'14), 2014. Munich, Germany. [pdf]
  • Does Badge-Based Learning Buck the Grading Curve? An Educational Experiment in Computer Architecture. P. Jamieson. FECS 2014. Las Vegas, NV. [pdf]
  • Getting Positional Play Data - It's, likely, in the crowd. L. Grace, B. Hunt, A. Heldt, P. Shine, M. Page, and P. Jamieson. CHI 2014 Workshop on HCI and Sports, 2014 [link-hci 2014][link-workshop]. Toronto, ON, Canada. [pdf]
  • More Graph Comparison Techniques on Mind Maps to Provide Students with Feedback Peter Jamieson. FIE'13, 2013 [link]. Oklahoma City, OK. [pdf]
  • Metaheuristic Entry Points for Harnessing Human Computation in Mainstream Games. Peter Jamieson, Lindsay Grace, Jack Hall, and Aditya Wibowo HCI International 2013 [link] Las Vegas, Nevada. [link]
  • Supergenes in a Genetic Algorithm for Heterogeneous FPGA Placement. Peter Jamieson, Farnaz Gharibian, and Lesley Shannon IEEE Congress on Evolutionary Computation, 2013 [link] Cancun, Mexico. [pdf]
  • Research Directions for Pushing Harnessing Human Computation to Mainstream Video Games. Peter Jamieson, Lindsay Grace, and Jack Hall. Meaningful Play, 2012 [link] East Lansing, Michigan. [pdf]
  • Using Modern Graph Analysis Techniques on Mind Maps to Help Quantify Learning Peter Jamieson. FIE'12, 2012. Seattle, WA. [pdf]
  • Using Simple Ancestry to Deter Inbreeding for Persistent Genetic Algorithm Search Aditya Wibowo and Peter Jamieson. International Conference on Genetic and Evolutionary Methods (GEM'12), 2012. Las Vegas, NV. [pdf]
  • The VTR Project: Architecture and CAD for FPGAs from Verilog to Routing Jonathan Rose, Jason Luu, Chi Wai Yu, Opal Densmore, Jeffrey Goeders, Andrew Somerville, Kenneth B. Kent, Peter Jamieson, and Jason H. Anderson International Symposium on Field Programmable Gate Arrays (FPGA'12), 2012. Monterey, California. pp 77-86. [pdf]
  • Power Consumption Benchmarking for Reconfigurable Platforms Teemu Pitkanen, Peter Jamieson, Tobias Becker, Sami Moisio, and Jarmo Takala. SDR '11 WInnComm, 2011. Washington, DC. [pdf]
  • Redblade: Miami University's Multifunctional Autonomous Robot Ryan Wolfarth, Steven Taylor, Aditya Wibowo, Brandon Williams, Yu Morton, and Peter Jamieson. ION GNSS Conference, 2011. Portland, OR. [pdf]
  • Early Project Based Learning Improvements via a "Star Trek Engineering Room" game framework, and competition Peter Jamieson. FIE'11, 2011. Rapid City, SD. [pdf]
  • Arduino for Teaching Embedded Systems. Are Computer Scientists and Engineering Educators Missing the Boat? Peter Jamieson. International Conference on Frontiers in Education: Computer Science and Computer Engineering (FECS'11), 2011. Las Vegas, NV. [pdf]
  • Exploring Inevitable Convergence for a Genetic Algorithm Persistent FPGA Placer Peter Jamieson. International Conference on Genetic and Evolutionary Methods (GEM'11), 2011. Las Vegas, NV. [pdf]
  • Scotty in the Engine Room - A Game to Help Learn Digital System Design. Peter Jamieson. Meaningful Play, 2010 [link] East Lansing, Michigan. [pdf]
  • Finding System-Level Information and Analyzing its Correlation to FPGA Placement. Farnaz Gharibian, Lesley Shannon and Peter Jamieson. 20th International Conference on Field Programmable Logic and Applications (FPL'10), 2010. Milano, Italy. [pdf]
  • The Mythical Creature Approach - A Simulation Alternative to Building Computer Architectures. Peter Jamieson, Darrel Davis, and Brooke Spangler. International Conference on Frontiers in Education: Computer Science and Computer Engineering (FECS'10), 2010. Las Vegas, NV. [pdf]
  • Revisiting Genetic Algorithms for the FPGA Placement Problem. Peter Jamieson. International Conference on Genetic and Evolutionary Methods (GEM'10), 2010. Las Vegas, NV. [pdf]
  • Persistent CAD for in-the-field Power Optimization. Peter Jamieson. The international conference on Engineering of Reconfigurable Systems and Algorithms (ERSA'10), 2010. Las Vegas, NV. [pdf]
  • Odin II - An Open-source Verilog HDL Synthesis tool for CAD Research. Peter Jamieson, Kenneth B. Kent, Farnaz Gharibian, and Lesley Shannon. 2010 Field-Programmable Custom Computing Machines (FCCM'10), 2010. Charlotte, North Carolina. [pdf] [ppt]
  • An Energy and Power Consumption Analysis of FPGA Routing Architectures. Peter Jamieson, Wayne Luk, Steve J.E. Wilton, and George A. Constantinides. Field-Programmable Technology, 2009. Sydney, Australia. [pdf]
  • Harnessing Human Computation Cycles for the FPGA Placement Problem. L. Terry, V. Roitch, S. Tufail, K. Singh, O. Taraq, W. Luk, and P. Jamieson, The international conference on Engineering of Reconfigurable Systems and Algorithms (ERSA'09), 2009. Las Vegas, Nevada. [pdf]
  • Benchmarking Reconfigurable Architectures in the Mobile Domain. Peter Jamieson, Tobias Becker, Teemu Pitkanen , Peter Y.K Cheung, Wayne Luk, and Tero Rissa, The Seventeenth Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'09), 2009. Napa Valley, California. [pdf] Presentation Slides [pdf]
  • VPR 5.0: FPGA CAD and Architecture Exploration Tools with Single-Driver Routing, Heterogeneity, and Process Scaling. Jason Luu, Ian Kuon, Peter Jamieson, Ted Campbell, Andy Ye, Mark Fang, and Jonathan Rose, International Symposium on Field Programmable Gate Arrays (FPGA'09), 2009. Monterey, California. pp 133-142. [pdf]
  • Power Characterization for the Fabric in Fine-Grain Reconfigurable Architectures. Tobias Becker, Peter Jamieson, Peter Y.K Cheung, Wayne Luk, and Tero Rissa. Southern Programmable Logic Conference (SPL'09), 2009 . [pdf]
  • Towards Benchmarking Energy Efficiency of Reconfigurable Architectures. Tobias Becker, Peter Jamieson, Wayne Luk, Peter Y.K. Cheung, and Tero Rissa. 18th International Conference on Field Programmable Logic and Applications (FPL'08), 2009 . Heidelberg, Germany [pdf]
  • Architecting Hard Crossbars on FPGAs and Increasing their Area-Efficiency with Shadow Clusters. Peter Jamieson and Jonathan Rose. IEEE International Conference on Field Programmable Technology (FPT07), 2007 , Kitakyushu, Japan, December 2007, pp. 57-64. [pdf]
  • Enhancing the area-efficiency of FPGAs with hard circuits using shadow clusters. Peter Jamieson and Jonathan Rose. IEEE International Conference on Field Programmable Technology, 2006 December, 2006, Pages 1-8. [pdf] Presentation Slides [pdf]
  • A Verilog RTL Synthesis Tool For Heterogeneous FPGAs. Peter Jamieson and Jonathan Rose. 15th International Conference on Field Programmable Logic and Applications, August, 2005. [pdf] Presentation Slides [pdf]
  • Mapping Multiplexers onto Hard Multipliers in FPGAs. Peter Jamieson and Jonathan Rose. In the Proceedings of the 3rd International IEEE-NEWCAS Conference.Quebec City , Quebec. June 19th-22nd, 2005. [pdf] Presentation Slides [pdf]
  • Jupiter/svm: a jvm-based single system image for clusters of workstations. C. Cavanna, T. Abdelrahman, A. Bilas, and P. Jamieson. Proceedings of the 16th International Conference on Parallel and Distributed Computing and Systems (PDCS2004), November, 2004. [pdf]
  • CableS: Thread Control and Memory Management Extensions for Shared Virtual Memory Clusters. Peter Jamieson and Angelos Bilas. 8th International Symposium on High-Performance Computer Architecture (HPCA-8). Cambridge, Massachusetts, February 2-6, 2002. [ps]
  • CableS: Thread Control and Memory System Extensions for Shared Virtual Memory Clusters. Peter Jamieson and Angelos Bilas. In the Proceedings of the Workshop on OpenMP Applications and Tools. Purdue University, West Lafayette, Indiana. July 30th-31st, 2001. [pdf]

POSTERS

  • Increasing the Area-Efficiency of Lower-Demand Hard Circuits in FPGAs using Shadow Clusters. Peter Jamieson and Jonathan Rose. FPGA - 2007. Montarey, CA.[pdf]
  • Improving Heterogeneous FPGAs by Maximizing Use of Hard Circuits. Peter Jamieson and Jonathan Rose. Design Automation Conference - 2006. San Francisco. Ph.D. Forum[pdf]
  • Odin: A Verilog RTL synthesis tool for heterogeneous FPGAs. Peter Jamieson and Jonathan Rose. Design Automation Conference - 2006. San Francisco. University Booth[pdf]

OTHER DOCUMENTS

  • [Abstract] The Need for Power Benchmarking of Reconfigurable Architectures. T. Becker, P. Jamieson, W. Luk, P.Y.K. Cheung, and T. Rissa. System-On-Chip (2008). [pdf]
  • Improving the Area Efficiency of Heterogeneous FPGAs with Shadow Clusters, Peter Jamieson Ph.D. Thesis, University of Toronto, 2007. [pdf]
  • CableS: Thread and Memory System Extensions to Support a Single Shared Virtual Memory Cluster Image. Peter Jamieson. University of Toronto, Masters of Applied Science Thesis. [ps]