Dr. J's Golden Rule 1 for Synthesizable Verilog

The Verilog language was originally created to test circuits.  The name "Verilog" comes from verifying logic.  Since this was the original intention of the language, not synthesizing logic, there are some constructs in the language, which confuse learners of Verilog.  This is why Golden Rule 1 was invented to help learners.  As you understand the details of Verilog you can forget this rule, but for beginners, if you remember and apply this rule your designs will have a much higher likelihood of working.

Golden Rule 1 states:

Declare all signals as "reg" if they are used on the Left-Hand-Side (LHS) of an statement in an always block.  Otherwise, if the signal is on the LHS then declare it as wire.

Why does this confuse some people?  The words wire and reg imply that a wire will be created for the word "wire" and a register for the word "reg".  This is not the case in synthesizable Verilog and is more related to the always blocks that the signal is used in.  For example, the following Verilog is written:
1. reg signal1;
2.  reg signal2;
3.
wire signal3;

4. assign signal3 = 1'b1;

5. always @(posedge clk or negedge rst)
6. begin

7.     signal2 <= signal1;
8. end

9.  always @(*)
10. begin

11.     signal1 = signal2;
12. end

When this circuit is synthesized into a logic circuit, signal1 and signal3 will be wires and signal2 will be a register.  This follows both golden rule 1 and golden rule 2, and the reality is that signal1, which is declared as a reg is actually a wire.

"Just follow this golden rule!", says Dr. J and your synthesized circuits will be Okay.