Dr. J's Golden Rule 2 for Synthesizable Verilog

The Verilog language was originally created to test circuits.  The name "Verilog" comes from verifying logic.  Since this was the original intention of the language, not synthesizing logic, there are some constructs in the language, which confuse learners of Verilog.  This is why Golden Rule 1 was invented to help learners.  As you understand the details of Verilog you can forget this rule, but for beginners, if you remember and apply this rule your designs will have a much higher likelihood of working.

Golden Rule 2 states:

Use the assignment operator "<=" in a sequential always block and the assignment operator "=" in combinational always blocks.

Why ?  Because in Verilog the two operators have different semantic meanings (how the computation is described).  Do a google search for blocking vs. non-blocking statements.  the problem again is the difference between synthesis and simulation.  Follow the rule and write your designs in this form and you will have a better time:

1. reg signal1;

2.  reg signal2;
wire signal3;

4. assign signal3 = 1'b1;

5. always @(posedge clk or negedge rst)
6. begin

7.     signal2 <= signal1;
8. end

9.  always @(*)
10. begin

11.     signal1 = signal2;
12. end

Line 7 uses the "<=" because it is in a sequential always block.  Lines 11 and 4 do not.  Line 11 is in a combinational always block.

"Just follow this golden rule!", says Dr. J and your synthesized circuits will be Okay.